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www.irf.com ? 2009 international rectifier 1 data sheet no. pd 97408b may 30, 2011 irs26072dspbf high and low side driver features ? floating channel designed for bootstrap operation ? integrated bootstrap diode suitable for compliment ary pwm switching schemes only ? irs26072dspbf is suitable for sinusoidal motor con trol applications ? irs26072dspbf is not recommended for trapezoidal motor control applications ? fully operational to 600 v ? tolerant to negative transient voltage, dv/dt immu ne ? gate drive supply range from 10 v to 20 v ? undervoltage lockout for both channels ? 3.3 v, 5 v, and 15 v input logic compatible ? matched propagation delay for both channels ? lower di/dt gate driver for better noise immunity ? outputs in phase with inputs ? rohs compliant typical applications ? motor control ? air conditioners/ washing machines ? general purpose inverters ? micro/mini inverter drivers product summary topology high and low side driver v offset 600 v v out 10 v C 20 v i o+ & i o (typical) 200 ma & 350 ma t on & t off (typical) 200 ns package options 8lead soic typical connection diagram vcc hin lin vcc hin lin com vb ho vs lo up to 600 v irs26072d to load
irs26072dspbf www.irf.com ? 2009 international rectifier 2 table of contents page description 3 simplified block diagram 3 typical application diagram 4 qualification information 5 absolute maximum ratings 6 recommended operating conditions 6 static electrical characteristics 7 dynamic electrical characteristics 7 functional block diagram 8 input/output pin equivalent circuit diagram 9 lead definitions 10 lead assignments 10 application information and additional details 11 parameter temperature trends 21 package details 26 tape and reel details 27 part marking information 28 ordering information 29
irs26072dspbf www.irf.com ? 2009 international rectifier 3 description the irs26072d is a high voltage, high speed power m osfet and igbt driver with independent high and low side referenced output channels. proprietary hvic a nd latch immune cmos technologies enable ruggedized monolithic construction. logic inputs are compatibl e with cmos or lsttl outputs, down to 3.3 v. the ou tput drivers feature a highpulse current buffer stage d esigned for minimum driver crossconduction. the fl oating channel can be used to drive nchannel power mosfet s or igbts in the high side configuration up to 600 v. simplified block diagram
irs26072dspbf www.irf.com ? 2009 international rectifier 4 typical application diagram
irs26072dspbf www.irf.com ? 2009 international rectifier 5 qualification information ? industrial ?? qualification level comments: this ic has passed jedec industrial qualification. ir consumer qualification level is granted by extension of the higher industrial level. moisture sensitivity level msl2 , 260 c (per ipc/jedec jstd020) human body model class 2 (per jedec standard jesd22a114) esd machine model class b (per eia/jedec standard eia/jesd22a115) ic latch-up test class i, level a (per jesd78) rohs compliant yes ? qualification standards can be found at internation al rectifiers web site http://www.irf.com/ ?? higher qualification ratings may be available shoul d the user have such requirements. please contact your international rectifier sales representative for fu rther information.
irs26072dspbf www.irf.com ? 2009 international rectifier 6 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all vo ltage parameters are absolute voltages referenced to com unless otherwise specified. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. symbol definition min. max. units v b high side floating supply voltage 0.3 620 v s high side floating supply offset voltage v b 20 ? v b + 0.3 v ho high side floating output voltage v s 0.3 v b + 0.3 v cc low side and logic fixed supply voltage 0.3 20 ? v lo low side output voltage 0.3 v cc + 0.3 v in logic and analog input voltages 0.3 v cc + 0.3 v pw hin highside input pulse width 500 ns dv s /dt allowable offset supply voltage slew rate 50 v/ns p d package power dissipation @ ta +25c 0.625 w rth ja thermal resistance, junction to ambient 200 c/w t j junction temperature 150 t s storage temperature 50 150 t l lead temperature (soldering, 10 seconds) 300 c ? all supplies are fully tested at 25 v. an internal 20 v clamp exists for each supply. recommended operating conditions for proper operation, the device should be used wit hin the recommended conditions. all voltage paramet ers are absolute voltages referenced to com unless otherwis e specified. the v s offset ratings are tested with all supplies biased at 15 v. symbol definition min. max. units v b high side floating supply voltage v s +10 v s + 20 v s static high side floating supply offset voltage ? 8 600 v s (t) transient high side floating supply offset volt age ?? 50 600 v ho high side floating output voltage v s v b v cc low side and logic fixed supply voltage 10 20 v lo low side output voltage 0 v cc v in logic input voltage 0 v cc v t a ambient temperature 40 125 c ? logic operation for v s of C8 v to 600 v. logic state held for v s of C8 v to Cv bs . ?? operational for transient negative v s of 50 v with a 50 ns pulse width. guaranteed by design. ref er to the application information section of this datasheet f or more details.
irs26072dspbf www.irf.com ? 2009 international rectifier 7 static electrical characteristics (v cc com) = (v b v s ) = 15 v and t a = 25 o c unless otherwise specified. the v in and i in parameters are referenced to com. the v o and i o parameters are referenced to com and v s and are applicable to the output leads lo and ho respectively. the v ccuv and v bsuv parameters are referenced to com and v s respectively. symbol definition min. typ. max. units test conditi ons v ih logic 1 input voltage 2.5 v il logic 0 input voltage 0.8 v in , th+ input positive going threshold 1.9 v in , th input negative going threshold 1 v oh high level output voltage 0.8 1.4 v ol low level output voltage 0.2 0.6 i o = 20 ma v ccuv+ v bsuv+ v cc and v bs supply undervoltage positive going threshold 8.0 8.9 9.8 v ccuv v bsuv v cc and v bs supply undervoltage negative going threshold 6.9 7.7 8.5 v ccuvh v bsuvh v cc and v bs supply undervoltage hysteresis 0.35 1.2 v i lk offset supply leakage current 1 50 v b =v s = 600 v i qbs quiescent v bs supply current 45 70 a i qcc quiescent v cc supply current 1.1 1.8 ma v in = 0 v or 5 v i in+ logic 1 input bias current 5 20 v in = 5 v i in logic 0 input bias current 2 a v in = 0 v i o+ output high short circuit pulsed current 120 200 i o output low short circuit pulsed current 250 350 ma v o = 0 v or 15 v pw 10 s r bs bootstrap resistance ?? 200 ?? integrated bootstrap diode is suitable for complime ntary pwm schemes only. irs26072d is suitable for sinusoidal motor control applications. irs26072d is not recommended for trapezoidal motor control applications. refer to the integrated bootstrap functionality sec tion of this datasheet for more details. dynamic electrical characteristics v cc = v b = 15 v, v s = com, t a = 25 o c and c l = 1000 pf unless otherwise specified. symbol definition min. typ. max. units test conditi ons t on turnon propagation delay 100 200 300 t off turnoff propagation delay 100 200 300 t r turnon rise time 150 220 t f turnoff fall time 50 80 mt t on , t off propagation delay matching time 50 v in = 0v and 5v pm pw pulse width distortion ? 75 ns pw input =10s ? pm is defined as pw in pw out .
irs26072dspbf www.irf.com ? 2009 international rectifier 8 functional block diagram uv detect pulse generator pulse filter hin hv level shifter q vs ho vb s r r uv detect delay lin vcc lo com integrated bs diode
irs26072dspbf www.irf.com ? 2009 international rectifier 9 input/output pin equivalent circuit diagrams
irs26072dspbf www.irf.com ? 2009 international rectifier 10 lead definitions symbol description vcc low side and logic power supply vb high side floating power supply vs high side floating supply return hin logic input for high side gate driver output ho , input is inphase with output lin logic input for low side gate driver output lo, input is inphase with output ho high side gate driver output lo low side gate driver output com low side supply return lead assignments
irs26072dspbf www.irf.com ? 2009 international rectifier 11 application information and additional details ? igbt/mosfet gate drive ? switching and timing relationships ? matched propagation delays ? input logic compatibility ? undervoltage lockout protection ? truth table: undervoltage lockout ? integrated bootstrap functionality ? bootstrap power supply design ? tolerant to negative v s transients ? pcb layout tips ? integrated bootstrap fet limitation ? additional documentation igbt/mosfet gate drive the irs26072d hvic is designed to drive high side a nd low side mosfet or igbt power devices. figures 1 and 2 show the definition of some of the relevant param eters associated with the gate driver output functi onality. the output current that drives the gate of the external power switches is defined as i o . the output voltage that drives the gate of the external power switches is defined as v ho for the high side and v lo for the low side; this parameter is sometimes generically called v out and in this case the high side and low side output voltages are not differentiated. figure 1: hvic sourcing current figure 2: hvic sinking current v s ( or com ) ho ( or lo ) v b ( or v cc ) i o + v ho ( or v lo ) + v s ( or com ) ho ( or lo ) v b ( or v cc ) i o
irs26072dspbf www.irf.com ? 2009 international rectifier 12 switching and timing relationships the relationship between the input and output signa ls of the irs26072d hvic is shown in figure 3. the definitions of some of the relevant parameters asso ciated with the gate driver input to output transmi ssion are given. figure 3: switching time waveforms during interval a of figure 4 the hvic receives the command to turn on both the high and low side swit ches at the same time; correspondingly, the high and low side s ignals ho and lo turn on simultaneously. figure 4: input/output timing diagram matched propagation delays the irs26072d hvic is designed for propagation dela y matching. with this feature, the input to output propagation delays t on , t off are the same for the low side and the high side ch annels; the maximum difference being specified by the delay matching parameter mt as defined in figure 6. lin or hin 50 % 50 % pw in pw out 10 % 10 % 90 % 90 % t off t on t r t f lo or ho
irs26072dspbf www.irf.com ? 2009 international rectifier 13 figure 6: delay matching waveform definition input logic compatibility the irs26072d hvic is designed with inputs compatib le with standard cmos and ttl outputs with 3.3 v an d 5 v logic level signals. figure 7 shows how an input signal is logically interpreted. figure 7: hin & lin input thresholds under-voltage lockout protection the irs26072d hvic provides undervoltage lockout p rotection on both the v cc low side and logic fixed power supply and the vbs high side floating power supply. figure 8 illustrates this concept by considering t he v cc (or v bs ) plotted over time: as the waveform crosses the uv lo threshold, the undervoltage protection is enter ed or exited. upon power up, should the v cc voltage fail to reach the v ccuv+ threshold, the gate driver outputs lo and ho will remain disabled. additionally, if the v cc voltage decreases below the v ccuv threshold during normal operation, the undervoltage lockout circuitry will shutdown the g ate driver outputs lo and ho. upon power up, should the v bs voltage fail to reach the v bsuv threshold, the gate driver output ho will remain disabled. additionally, if the v bs voltage decreases below the v bsuv threshold during normal operation, the under voltage lockout circuitry will shutdown the high si de gate driver output ho.
irs26072dspbf www.irf.com ? 2009 international rectifier 14 the uvlo protection ensures that the hvic drives ex ternal power devices only with a gate supply voltag e sufficient to fully enhance them. without this prot ection, the gates of the external power switches co uld be driven with a low voltage, which would result in power swi tches conducting current while with a high channel impedance, which would produce very high conduction losses pos sibly leading to power device failure. figure 8: uvlo protection truth table: under-voltage lockout table 2 provides the truth table for the irs26072d hvic. the 1 st line shows that for v cc below the uvlo threshold both the gate driver outp uts lo and ho are disabled. a fter v cc returns above v ccuv , the gate driver outputs return functional. the 2 nd line shows that for v bs below the uvlo threshold, the gate driver output h o is disabled. after v bs returns above v bsuv , ho remains low until a new rising transition of h in is received. the last line shows the normal operation of the hvi c. outputs vcc vbs lo ho uvlo v cc < v ccuv 0 0 uvlo v bs 15 v < v bsuv lin 0 normal operation 15 v 15 v lin hin table 2: uvlo truth table v ccuv ( or v bsuv ) uvlo protection ( gate driver outputs disabled ) normal operation normal operation v ccuv + ( or v bsuv + ) v cc ( or v bs ) time
irs26072dspbf www.irf.com ? 2009 international rectifier 15 integrated bootstrap functionality the irs26072d hvic embeds an integrated bootstrap f et that eliminates the need of external bootstrap d iodes and resistors allowing an alternative drive of the bootstrap supply for a wide range of applications. a bootstrap fet is connected between the high side floating power supply vb and the low side and logic fixed power supply vcc (see fig. 9). figure 9: simplified bootstrap fet connection the bootstrap fet is suitable for complimentary pwm switching schemes only. complimentary pwm refers t o pwm schemes where the hin & lin input signals are a lternately switched on and off. irs26072d is suitab le for sinusoidal motor control and the integrated bootstr ap feature can be used either in parallel with the external bootstrap network (diode and resistor) or as a repl acement of it. the use of the integrated bootstrap as a replacement of the external bootstrap network may h ave some limitations at very high pwm duty cycle, corresponding to very short lin pulses, due to the bootstrap fet equivalent resistance r bs . irs26072d is not recommended for trapezoidal motor control, even if an external bootstrap network is employed in parall el. the bootstrap fet is conditioned as follows: ? bootstrap turnsoff (immediately) or stays off whe n either: ho goes/stays high; v b goes/ stays high (> 1.1*v cc ); ? bootstrap turnson when: lo is high (low side is on) and v b is low (<1.1*v cc ); lo and ho are low after a transition of lin from high to low and v b goes low (<1.1*v cc ) before a fixed time of 20us; lo and ho are low after a transition of hin from high to low and v b goes low (<1.1*v cc ) before a retriggerable time of 20us. in this case the tim e counter is kept in reset state until vb goes high (>1.1v cc ). in figure 10 the bootfet timing diagram details are represented. v cc v b bootstrap fet
irs26072dspbf www.irf.com ? 2009 international rectifier 16 + vb 1.1*vcc hin lin bootstrap fet 20 us timer counter timer is reset timer is reset timer expired figure 10: bootfet timing diagram bootstrap power supply design for information related to the design of the bootst rap power supply while using the integrated bootstr ap functionality of the irs26072d, please refer to app lication note 1123 (an1123) entitled bootstrap ne twork analysis: focusing on the integrated bootstrap func tionality. this application note is available at www.irf.com . for information related to the design of a standard bootstrap power supply (i.e., using an external di screte diode) please refer to design tip 044 (dt044) entitled using monolithic high voltage gate drivers. this design tip is available at www.irf.com .
irs26072dspbf www.irf.com ? 2009 international rectifier 17 tolerant to negative vs transients a common problem in todays highpower switching co nverters is the transient response of the switch no des voltage as the power devices switch on and off quic kly while carrying a large current. a typical 3pha se inverter circuit is shown in figure 11; where we define the power switches and diodes of the inverter. if the highside switch (e.g., the igbt q1 in figur es 12 and 13) switches off, while the u phase curre nt is flowing to an inductive load, a current commutation occurs from highside switch (q1) to the diode (d2) in par allel with the lowside switch of the same inverter leg. at the sa me instance, the voltage node v s1 , swings from the positive dc bus voltage to the negative dc bus voltage. figure 11: three phase inverter q1 on d2 v s1 q2 off i u dc+ bus dc bus figure 12: q1 conducting figure 13: d2 conducting also when the v phase current flows from the induct ive load back to the inverter (see figures 14 and 1 5), and q4 igbt switches on, the current commutation occurs from d3 to q4. at the same instance, the voltage node, v s2 , swings from the positive dc bus voltage to the nega tive dc bus voltage.
irs26072dspbf www.irf.com ? 2009 international rectifier 18 figure 14: d3 conducting figure 15: q4 conducting however, in a real inverter circuit, the v s voltage swing does not stop at the level of the ne gative dc bus, rather it swings below the level of the negative dc bus. this undershoot voltage is called negative v s transient. the circuit shown in figure 16 depicts one leg of t he three phase inverter; figures 17 and 18 show a s implified illustration of the commutation of the current betw een q1 and d2. the parasitic inductances in the pow er circuit from the die bonding to the pcb tracks are lumped t ogether in l c and l e for each igbt. when the highside switch is on, v s1 is below the dc+ voltage by the voltage drops asso ciated with the power switch and the parasitic elements of the circuit. when the highside power s witch turns off, the load current momentarily flows in the low side freewheeling diode due to the inductive load c onnected to v s1 (the load is not shown in these figures). this current flows from the dc bus (which is connected to the com pin of the hvic) to the load and a negat ive voltage between v s1 and the dc bus is induced (i.e., the com pin of t he hvic is at a higher potential than the v s pin). figure 16: parasitic elements figure 17: v s positive figure 18: v s negative in a typical motor drive system, dv/dt is typically designed to be in the range of 35 v/ns. the negat ive v s transient voltage can exceed this range during some events su ch as short circuit and overcurrent shutdown, when di/dt is greater than in normal operation. international rectifiers hvics have been designed for the robustness required in many of todays dema nding applications. an indication of the irs26072ds robu stness can be seen in figure 19, where there is rep resented the irs26072d safe operating area at v bs =15v based on repetitive negative v s spikes. a negative v s transient voltage falling in the grey area (outside soa) may lead to ic permanent damage; vice versa unwanted fu nctional anomalies or permanent damage to the ic do not appe ar if negative vs transients fall inside soa.
irs26072dspbf www.irf.com ? 2009 international rectifier 19 at v bs =15v in case of v s transients greater than 16.5 v for a period of ti me greater than 50 ns; the hvic will hold by design the highside outputs in the off sta te for 4.5 s. figure 19: negative v s transient soa @ vbs=15v even though the irs26072d has been shown able to ha ndle these large negative vs transient conditions, it is highly recommended that the circuit designer always limit the negative v s transients as much as possible by careful pcb layout and component use.
irs26072dspbf www.irf.com ? 2009 international rectifier 20 pcb layout tips distance between high and low voltage components: its strongly recommended to place the components tied to the floating voltage pins (v b and v s ) near the respective high voltage portions of the device. please see the case outline information in this datasheet for the detai ls. ground plane: in order to minimize noise coupling, the ground pl ane should not be placed under or near the high voltage floating side. gate drive loops: current loops behave like antennas and are able to receive and transmit em noise (see figure 20). in order to reduce the em coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as much as possible. moreover , current can be injected inside the gate drive loo p via the igbt collectortogate parasitic capacitance. the p arasitic autoinductance of the gate loop contribut es to developing a voltage across the gateemitter, thus increasing the possibility of a self turnon effect . figure 20: antenna loops supply capacitor: it is recommended to place a bypass capacitor betw een the vcc and com pins. this connection is shown in figure 21. a ceramic 1 f ce ramic capacitor is suitable for most applications. this component should be placed as close as possible to the pins in order to reduce parasitic elements. hin 1 , 2 , 3 lin 1 , 2 ,3 ho 1 , 2 , 3 lo 1 , 2 , 3 up to 6 00v vcc lin 1 , 2 ,3 hin 1 , 2 , 3 to load v b 1 , 2 , 3 v s 1 , 2 , 3 vcc gnd com figure 21: supply capacitor r g v ge gate drive loop c gc i gc v b ( or v cc ) ho ( or lo ) v s ( or com )
irs26072dspbf www.irf.com ? 2009 international rectifier 21 routing and placement: power stage pcb parasitic elements can contribute to large negative voltage transients at the switch node; it is recommended to limit the pha se voltage negative transients. in order to avoid s uch conditions, it is recommended to 1) minimize the hi ghside source to lowside collector distance, and 2) minimize the lowside emitter to negative bus rail stray ind uctance. however, where negative v s spikes remain excessive, further steps may be taken to reduce the spike. thi s includes placing a resistor (5 or less) between the v s pin and the switch node (see figure 22), and in some ca ses using a clamping diode between com and v s (see figure 23). see dt044 at www.irf.com for more detailed information. figure 22: v s resistor figure 23: v s clamping diode integrated bootstrap fet limitation the integrated bootstrap fet functionality has an o perational limitation under the following bias cond itions applied to the hvic: ? vcc pin voltage = 0v and ? vs or vb pin voltage > 0 in the absence of a vcc bias, the integrated bootst rap fet voltage blocking capability is compromised and a current conduction path is created between vcc & vb pins, a s illustrated in fig.24 below, resulting in power l oss and possible damage to the hvic. figure 24: current conduction path between vcc and vb pin to load v s ho v b lo com r vs dc + bus dc bus c bs to load v s ho v b lo com r vs d vs dc + bus dc bus c bs
irs26072dspbf www.irf.com ? 2009 international rectifier 22 relevant application situations: the above mentioned bias condition may be encounter ed under the following situations: ? in a motor control application, a permanent magnet motor naturally rotating while vcc power is off. i n this condition, back emf is generated at a motor te rminal which causes high voltage bias on vs nodes resulting unwanted current flow to vcc. ? potential situations in other applications where v s/vb node voltage potential increases before the vc c voltage is available (for example due to sequencing delays in smps supplying vcc bias) application workaround: insertion of a standard pn junction diode between vcc pin of ic and positive terminal of vcc capacito rs (as illustrated in fig.25) prevents current conduction outof vcc pin of gate driver ic. it is important not to connect the vcc capacitor directly to pin of ic. diode selectio n is based on 25v rating or above & current capabil ity aligned to icc consumption of ic 100ma should cover most app lication situations. as an example, part number # l l4154 from diodes inc (25v/150ma standard diode) can be u sed. figure 25: diode insertion between vcc pin and vcc capacitor note that the forward voltage drop on the diode ( v f ) must be taken into account when biasing the vcc p in of the ic to meet uvlo requirements. vcc pin bias = vcc supply voltage C v f of diode . additional documentation several technical documents related to the use of h vics are available at www.irf.com ; use the site search function and the document number to quickly locate them. below is a short list of some of these docum ents. dt973: managing transients in control ic driven po wer stages an1123: bootstrap network analysis: focusing on th e integrated bootstrap functionality dt044: using monolithic high voltage gate drivers an978: hv floating mosgate driver ics parameter temperature trends figures 2643 provide information on the experiment al performance of the irs26072d hvic. the line plot ted in each figure is generated from actual experimenta l data. a small number of individual samples were t ested at three temperatures (40 oc, 25 oc, and 125 oc) i n order to generate the experimental curve. the lin e consist of three data points (one data point at each of the tested temperatures) that have been connected toge ther to illustrate the understood temperature trend. the in dividual data points on the curve were determined b y calculating the averaged experimental value of the parameter (for a given temperature). vcc vss (or com) vb vcc capacitor vcc vss (or com) vb vcc capacitor
irs26072dspbf www.irf.com ? 2009 international rectifier 23 0.0 0.2 0.4 0.6 0.8 1.0 50 25 0 25 50 75 100 125 tem perature ( o c) iqcc (ma) 0 20 40 60 80 100 50 25 0 25 50 75 100 125 tem perature ( o c) iqbs (ua) figure 26: i qcc vs. temperature figure 27: i qbs vs. temperature 0 2 4 6 8 10 50 25 0 25 50 75 100 125 tem perature ( o c) ilk (ua) 0 2 4 6 8 10 50 25 0 25 50 75 100 125 tem perature ( o c) iin+ (ua) figure 28: i lk vs. temperature figure 29: i in+ vs. temperature 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) ton (ns) 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 tem perature ( o c) toff (ns) figure 30: t on vs. temperature figure 31: t off vs. temperature
irs26072dspbf www.irf.com ? 2009 international rectifier 24 0 40 80 120 160 200 50 25 0 25 50 75 100 125 tem perature ( o c) trise (ns) 0 20 40 60 80 100 50 25 0 25 50 75 100 125 tem perature ( o c) tfall (ns) figure 32: t rise vs. temperature figure 33: t fall vs. temperature 0 20 40 60 80 100 50 25 0 25 50 75 100 125 tem perature ( o c) mt (ns) 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 tem perature ( o c) rbs (ohm) figure 34: mt vs. temperature figure 35: r bs vs. temperature 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) io+ (ma) 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 tem perature ( o c) io- (ma) figure 36: i o+ vs. temperature figure 37: i o- vs. temperature
irs26072dspbf www.irf.com ? 2009 international rectifier 25 0 2 4 6 8 10 50 25 0 25 50 75 100 125 tem perature ( o c) vccuv- (v) 0 2 4 6 8 10 50 25 0 25 50 75 100 125 tem perature ( o c) vbsuv- (v) figure 38: v ccuv- vs. temperature figure 39: v bsuv- vs. temperature 0 2 4 6 8 10 50 25 0 25 50 75 100 125 tem perature ( o c) vccuv+ (v) 0 2 4 6 8 10 50 25 0 25 50 75 100 125 tem perature ( o c) vbsuv+ (v) figure 40: v ccuv+ vs. temperature figure 41: v bsuv+ vs. temperature 0.0 0.4 0.8 1.2 1.6 2.0 50 25 0 25 50 75 100 125 tem perature ( o c) vccuvh (v) 0.0 0.4 0.8 1.2 1.6 2.0 50 25 0 25 50 75 100 125 tem perature ( o c) vbsuvh (v) figure 42: v ccuvh vs. temperature figure 43: v bsuvh vs. temperature
irs26072dspbf www.irf.com ? 2009 international rectifier 26 package details
irs26072dspbf www.irf.com ? 2009 international rectifier 27 tape and reel details e f a c d g a b h note : controlling dim ension in m m loaded tape feed direction a h f e g d b c carrier tape dimension for 8soicn code min max min max a 7.90 8.10 0.311 0.318 b 3.90 4.10 0.153 0.161 c 11.70 12.30 0.46 0.484 d 5.45 5.55 0.214 0.218 e 6.30 6.50 0.248 0.255 f 5.10 5.30 0.200 0.208 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 8soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 18.40 n/a 0.724 g 14.50 17.10 0.570 0.673 h 12.40 14.40 0.488 0.566 metric imperial
irs26072dspbf www.irf.com ? 2009 international rectifier 28 part marking information
irs26072dspbf www.irf.com ? 2009 international rectifier 29 ordering information standard pack base part number package type form quantity complete part number tube/bulk xxx irs26072d spbf irs26072d soic 8 tape and reel xxx irs26072d strpbf the information provided in this document is believ ed to be accurate and reliable. however, internatio nal rectifier assumes no responsibility for the consequences of the use of this information. inter national rectifier assumes no responsibility for an y infringement of patents or of other rights of thi rd parties which may result from the use of this infor mation. no license is granted by implication or ot herwise under any patent or patent rights of intern ational rectifier. the specifications mentioned in this do cument are subject to change without notice. this document supersedes and replaces all information previously supplied. for technical support, please contact irs technica l assistance center http://www.irf.com/technical-info/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105
irs26072dspbf www.irf.com ? 2009 international rectifier 30 revision history revision date change comments prelim. presumably a copy of irs2607d datasheet 01 30 apr 09 preliminary with input filter removed 02 02 jul 09 formatting of irs2334 datasheet, secti ons copied and added from irs26042d datasheet, parameters limits checked against test l imits 03 13jul09 date and datasheet pd number added 04 18aug09 updated to reflect that integrated boo tstrap diode works only with complimentary pwm. and also added not recommended for trapezoidal mot or control 05 18aug09 released by ramanan 06 21aug09 parameter temperature trend graphs upd ated, first page footer updated 07 30may11 added bootstrap fet limitation

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